Japanese Patent Application No. 2001-165449, filed on May 31, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor memory device including memory cells, each having two nonvolatile memory elements controlled by one word gate and two control gates.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or Metal-Oxide-Nitride-Oxide-Substrate) device is known. In the MONOS nonvolatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film, and silicon oxide film. Charges are trapped in the silicon nitride film.
The MONOS nonvolatile semiconductor memory device is disclosed in literature (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123). This literature discloses a twin MONOS flash memory cell including two nonvolatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites.
In order to drive the twin MONOS flash memory cell, two bit lines, one word line, and two control gate lines are necessary.
Of these interconnects, two bit lines and two control gate lines are generally wired in the column direction. However, it is difficult to provide four interconnects (two bit lines and two control gate lines) within the width of a plurality of memory cells in one column using the same metal interconnect layer even in the case of using a photolithographic process with a minimum line and space width.
Therefore, the wiring space must be secured by increasing the width of the memory cells in one column. However, this causes a decrease in the degree of integration of the memory cells, whereby it is impossible to deal with a recent increase in the capacity of the nonvolatile semiconductor memory device.
The present invention may provide a highly integrated nonvolatile semiconductor memory device in which one memory cell has two trap sites.
The present invention may also provide a nonvolatile semiconductor memory device capable of securing the degree of margin and freedom relating to the arrangement of interconnects by decreasing the number of interconnects for supplying electric power to control gates.
Further, the present invention may provide a nonvolatile semiconductor memory device capable of securing the degree of margin and freedom relating to the arrangement of interconnects for the control gates and bit lines.
A nonvolatile semiconductor memory device according to one aspect of the present invention comprises a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates. The memory cell array region includes a plurality of control gate lines formed by connecting, in the first direction, each of the control gates of the memory cells in each column arranged in the first direction, and sub control gate lines extending in the first direction in an upper layer of the plurality of control gate lines, the number of sub control gate lines being half the number of control gate lines. Each two control gate lines adjacent across the boundaries between the plurality of memory cells in the second direction are connected in common with one sub control gate line.
In this aspect of the present invention, the number of the sub control gates can be decreased to approximately half the number of the control gates. This produces a surplus of space for interconnects in a layer in which the sub control gate lines are disposed, whereby the degree of freedom for the interconnects can be increased.
Therefore, there is no need to decrease the degree of integration in order to secure space for metal interconnects even if one memory cell has two trap sites, whereby a highly integrated nonvolatile semiconductor memory device can be provided.
The nonvolatile semiconductor memory device may further comprise a select region disposed adjacent to the memory cell array region in the first direction, and a plurality of main control gate lines extending in the first direction within the select region and the memory cell array region, the number of the main control gate lines being smaller than the number of the sub control gate lines. This select region may have at least one sub control gate select circuit which selectively connects the sub control gate lines with the main control gate lines.
Since this enables the number of the main control gate lines to be smaller than the number of the sub control gate lines, a surplus of space for interconnects is produced in a layer in which the main control gate lines are disposed, whereby the degree of freedom for interconnects can be increased.
The select region may include first and second select regions disposed on both sides of the memory cell array region in the first direction. In this case, a first sub control gate select circuit which selectively connects one of an odd-numbered sub control gate line and an even-numbered sub control gate line with the plurality of main control gate lines may be provided in the first select region. A second sub control gate select circuit which selectively connects the other one of the odd-numbered sub control gate line and the even-numbered sub control gate line with the plurality of main control gate lines may be provided in the second select region.
The degree of freedom for interconnects of the sub control gate lines is further increased by dividing the select region, to which the plurality of sub control gate lines extends, in two.
In a nonvolatile semiconductor memory device according to another aspect of the present invention, the memory cell array region comprises sub control gate lines extending in the first direction in an upper layer of the plurality of control gate lines, the number of sub control gate lines being the same as the number of bit lines, and a plurality of word lines extending in the second direction. In this case, each two control gate lines adjacent across the boundaries between the plurality of memory cells in the second direction are connected in common with one sub control gate line.
According to this aspect of the present invention, the number of the sub control gate lines is the same as the number of the bit lines. Therefore, the width of the line and space can be designed in common between a layer in which the bit lines are formed and a layer in which the sub control gate lines are formed.
Each two control gate lines, disposed on both sides of an even-numbered sub bit line, may be connected in common with an even-numbered sub control gate line. Each two control gate lines, disposed on both sides of an odd-numbered sub bit line, may be connected in common with an odd-numbered sub control gate line.
Each of the bit lines may be divided into a plurality of bit split lines in the first direction by a discontinuous region. In this case, a plurality of sub bit lines connected respectively with the plurality of bit split lines which form one bit line may be provided. With this configuration, the bit lines divided in the first direction can be backed with the sub bit lines.
The nonvolatile semiconductor memory device may further comprise first and second select regions formed on both sides of the memory cell array region in the first direction, a plurality of main control gate lines extending in the first direction within the first and second select regions and the memory cell array region, the number of the main control gate lines being smaller than the number of the sub control gate lines, and a plurality of main bit lines extending in the first direction within the first and second select regions and the memory cell array region, the number of the main bit lines being smaller than the number of the sub bit lines.
This enables the number of main bit lines and the number of main control gate lines to be decreased, whereby a surplus of space for interconnects is produced because the total number of the interconnects decreases even if the main bit lines and the main control gate lines are disposed in the same layer.
Specifically, the main bit lines and the main control gate lines may be a third metal interconnect layer, for example.
Moreover, the degree of freedom for each interconnects is further increased by dividing the select region, to which the sub bit lines and the sub control gate lines extend, in two.
In this case, the first select region may comprise a first sub bit select circuit which selectively connects one of the odd-numbered sub bit line and the even-numbered sub bit line with the main bit lines, and a first sub control gate select circuit which selectively connects one of the odd-numbered sub control gate line and the even-numbered sub control gate line with the main control gate lines. The second select region may comprise a second sub bit select circuit which selectively connects the other one of the odd-numbered sub bit line and the even-numbered sub bit line with the main bit lines, and a second sub control gate select circuit which selectively connects the other one of the odd-numbered sub control gate line and the even-numbered sub control gate line with the main control gate lines.
Since the sub bit select circuits and the sub control gate select circuits can be dispersed in the first and second select regions in this manner, the circuit layout is facilitated.
A plurality of memory blocks each of which is formed of the memory cell array region and the first and second select regions provided on both sides of the memory cell array region may be arranged in the first direction. This enables an increase in the storage capacity of the nonvolatile semiconductor memory device. Moreover, since the length of the sub control gate lines and the sub bit lines can be decreased, an interconnect capacitance can be reduced. Furthermore, since data can be collectively erased in the block unit, the erase unit can be reduced in comparison with the case of erasing data over the entire memory.
In this case, a main bit line driver which drives the plurality of main bit lines may be provided on one end of the arranged memory blocks in the first direction.
This enables the plurality of main bit lines to be shared by the plurality of memory blocks, and the main bit line driver to be shared by the plurality of memory blocks.
A main control gate line driver which drives the plurality of main control gate lines may be provided on the other end of the arranged memory blocks in the first direction.
This enables the plurality of main control gate lines to be shared by the plurality of memory blocks, and the main control gate line driver to be shared by the plurality of memory blocks.
A word line driver which drives the word lines may be provided on one end of the arranged memory blocks in the second direction. In order to further increase the storage capacity of the nonvolatile semiconductor memory device, the plurality of memory blocks may be disposed on both sides in the second direction with the word line driver interposed therebetween.
Each of the two nonvolatile memory elements may have an ONO film consisting of an oxide film (O), nitride film (N), and oxide film (O) as a charge trap site. However, other types of structures may be employed.